Sharif Univ., Tehran, Iran +98-21-6616-6614 sbayat AT sharif.edu

List of 3S-Lab Patents:


  1. Siavash Bayat-Sarmadi, Shahriar Ebrahimi, Hatameh Mosanaei Boorani “A Quantum-resistant cryptoprocessing”, US Patent App. 16/807,394, 2020.

List of 3S-Lab Publications:


  1. S. Ebrahimi, S. Bayat-Sarmadi, “A Lightweight Fuzzy Extractor Based on LPN Problem for Device and Biometric Authentication in IoT”,IEEE Internet of Things Journal, to appear.

  2. M.H. Farzam, S. Bayat-Sarmadi, H. Mosannaei-Boorani, Armin Alivand, “Hardware Architecture for Supersingular Isogeny Diffie-Hellman and Key Encapsulation Using a Fast Montgomery Multiplier”,IEEE Transactions on Circuits and Systems I, 2021.

  3. N. Shekofte, S. Bayat-Sarmadi, H. Mosannaei-Boorani, “A Trusted Design Platform for Trojan Detection in FPGA Bitstreams Using Partial Reconfiguration”,ISC International Journal of Information Security (ISeCure), 2021.

  4. M. Salehi, S. Bayat-Sarmadi, “PLCDefender: Improving Remote Attestation Techniques for PLCs using Physical Model”, IEEE Internet of Things Journal, 2020.

  5. ME. Mazaheri, F. Taheri, S. Bayat Sarmadi, “Lurking Eyes: A Method to Detect Side-Channel Attacks on JavaScript and WebAssembly”, International ISC Conference on Information Security and Cryptology (ISCISC), 2020.

  6. S. Ebrahimi, S. Bayat-Sarmadi, “Lightweight and Fault Resilient Implementations of Binary Ring-LWE for IoT Devices”, International Symposium on Computer Architecture and Digital Systems (CADS), 2020.

  7. MH Farzam, S Bayat-Sarmadi, H Mosanaei-Boorani, “Implementation of Supersingular Isogeny-Based Diffie-Hellman and Key EncapsulationUsing an Efficient Scheduling”, IEEE Transactions on Circuits and Systems I, 2020.

  8. S. Ebrahimi, S. Bayat-Sarmadi, “Lightweight and Fault Resilient Implementations of Binary Ring-LWE for IoT Devices”, IEEE Internet of Things Journal, 2020.

  9. S. Ebrahimi, S. Bayat-Sarmadi, H. Mosanaei-Boorani, “Post-Quantum Cryptoprocessors Optimized for Edge and Resource-Constrained Devices in IoT”, IEEE Internet of Things Journal, 2019.

  10. O. Ranjbar, S. Bayat-Sarmadi, F. Pooyan, H. Asadi, “A Unified Approach to Detect and Distinguish Hardware Trojans and Faults in SRAM-based FPGAs”, journal of Electronic Testing Theory and Applications (JETTA), 2019.

  11. A. Boorghany, S. Bayat-Sarmadi, R. Jalili, “Practical Provably-Secure Authenticated Encryption Schemes Using Lattice-based Pseudorandom Function SPRING”, Scientia Iranica Journal, 2019.

  12. Taha Shaahroodi, Siavash Bayat-Sarmadi, Hatameh Mosanaei-Boorani, “Low-Latency Double Point Multiplication Architecture Using Differential Addition Chain over GF(2m)”, IEEE Transactions on Circuits and Systems I: Regular Papers, 2019.

  13. Mehran Mozaffari Kermani, Siavash Bayat-Sarmadi, and Reza Azarderakhsh, “High-Performance Fault Diagnosis Schemes for Efficient Hash Algorithm BLAKE”, IEEE LatinCAS conference, 2019.
  14. M AshrafiAmiri, AHA Zargari, SMH Farzam, S Bayat-Sarmadi “Towards side channel secure cyber-physical systems”, Real-Time and Embedded Systems and Technologies (RTEST), 31-38, 2018.

  15. MM Kermani, R Azarderakhsh, S Bayat-Sarmadi, “Reliable hardware architectures for efficient secure hash functions ECHO and fugue”, Proceedings of the 15th ACM International Conference on Computing Frontiers. ACM, 2018.

  16. Raziyeh Salarifard, Siavash Bayat-Sarmadi, and Hatameh Mosanaei-Boorani, "A Low-Latency and Low-Complexity Point-Multiplication in ECC", IEEE Transactions on Circuits and Systems I: Regular Papers, to appear, 2018.

  17. Mohammad Hossein Yalame, Mohammad Hossein Farzam, Siavash Bayat Sarmadi, "Secure Two-Party Computation Using an Efficient Garbled Circuit by Reducing Data Transfer", 23-34, ATIS 2017.

  18. Raziyeh Salarifard, Siavash Bayat-Sarmadi, and Mohammad Farmani, “High-Throughput Low-Complexity Unified Multipliers Over GF(2m) in Dual and Triangular Bases”, IEEE Transactions on Circuit and Systems I, Sep. 2016.

  19. Reza Azarderakhsh, Mehran Mozaffari Kermani, Siavash Bayat-Sarmadi, and Chiou-Yng Lee, “Systolic Gaussian Normal Basis Multiplier Architectures Suitable for High-Performance Applications”, IEEE Transactions on VLSI Systems, 23(9),1969-1972, Sept. 2015.

  20. B. Khaleghi, A. Ahari, H. Asadi, S. Bayat-Sarmadi, “FPGA-based Protection Scheme against Hardware Trojan Horse Insertion Using Dummy Logic”, IEEE Embedded Systems Letters, 7(2): 46-50, June 2015.

  21. A. Boorghany, S. Bayat-Sarmadi, R. Jalili, “On Constrained Implementation of Lattice-based Cryptographic Primitives and Schemes on Smart Cards”, ACM Transactions on Embedded Computing Systems (SI: Embedded Platforms for Cryptography in the Coming Decade), 14(3), Article 42, 25 pages, April 2015.

  22. S. Bayat-Sarmadi, M. Farmani, “High-Throughput Low-Complexity Systolic Montgomery Multiplication Over GF(2^m) based on Trinomials”, IEEE Transactions on Circuits and Systems II, 62(4): 377-381, January 2015.

  23. M. Mozaffari Kermani, K. Tian, R. Azarderakhsh, S. Bayat Sarmadi, "Fault-Resilient Lightweight Cryptographic Block Ciphers for Secure Embedded Systems," IEEE Embedded Systems Letters, 6(4): 89-92, October 2014.

  24. S. Bayat-Sarmadi, M. Mozaffari-Kermani, A. Reyhani-Masoleh, “Efficient and Concurrent Reliable Realization of the Secure Cryptographic SHA-3 Algorithm”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 33(7):1105-1109, July 2014.

  25. Mehran Mozaffari Kermani, Reza Azarderakhsh, Chiou-Yng Lee, and Siavash Bayat-Sarmadi, “Reliable Concurrent Error Detection Architectures for Extended Euclidean-based Division over GF(2m)”, IEEE Transactions on VLSI Systems, 22(5):995-1003, May 2014.

  26. S. Bayat-Sarmadi, M. Mozaffari-Kermani, Reza Azarderakhsh, and Chiou-Yng Lee, “A Dual Basis Super-Serial Multiplier Suitable for Lightweight Cryptographic Applications", IEEE Transactions on Circuits and Systems II, 61(2):125-129, Feb 2014.

  27. S. Bayat-Sarmadi and M. A. Hasan, “Concurrent Error Detection in Finite Field Arithmetic Operations using Pipelined and Systolic Architectures”, IEEE Transactions on Computers,58(11): 1553-1567, Nov. 2009.

  28. S. Bayat-Sarmadi and M. A. Hasan, “Detecting Errors in a Polynomial Basis Multiplier Using Multiple Parity Bits for Both Inputs”, in proceeding of the 25th IEEE International Conference on Computer Design (ICCD), 2007.

  29. S. Bayat-Sarmadi and M. A. Hasan, “Run-Time Error Detection in Polynomial Basis Multiplication Using Linear Codes”, in proceeding of the 18th IEEE International ASAP Conference, 2007.

  30. S. Bayat-Sarmadi and M. A. Hasan, “On Concurrent Detection of Errors in Polynomial Basis Multiplication”, IEEE Transactions on VLSI Systems, 15(4):413-426, April 2007

Other Publications:


  1. S. Bayat-Sarmadi, “Timing Analysis of the Solutions of the Discrete-Time Wiener-Hopf Equations”, in proceeding of the International Conference for Upcoming Engineers (ICUE), 2006.

  2. S. Bayat-Sarmadi and M. A. Hasan, “Concurrent Error Detection of Polynomial Basis Multiplication over Extension Fields using a Multiple-bit Parity Scheme”, in proceeding of the IEEE International Symposium on Defect and fault Tolerance in VLSI Systems (DFT), 2005.

  3. A.R. Ejlali, S.G. Miremadi, H.R. Zarandi, G. Asadi, and S. Bayat-Sarmadi, “A Hybrid Fault Injection Approach Based on Simulation and Emulation Co-operation”, in proceeding of the IEEE International Conference on Dependable Systems and Networks (DSN), 2003.

  4. S. Bayat-Sarmadi, M. Röser, and D. Tavangarian, “Metadata as a Basis for Automatic Generation of Learning Documents”, in proceeding of the Workshop on Interactive Computer Aided Learning - Learning Objects & Reusability of Content (ICL) 2003.

  5. S.G. Miremadi, S. Bayat-Sarmadi, and G. Asadi, “Speedup Analysis in Simulation-Emulation Co-Operation”, in proceeding of the IEEE International Conference on Field programmable Technology (FPT), 2002.

  6. S. Bayat-Sarmadi, S.G. Miremadi, G. Asadi, and A. R. Ejlali, “Fast Prototyping with Co-Operation of Simulation and Emulation”, in proceeding of the 12th International Conference on Field Programmable Logic and Applications (FPL), 2002.

  7. S. Hessabi, A. Ahmadinia, G. Asadi, S. Bayat-Sarmadi , and M. Gudarzi, “Co-FFT Design: FFT Implementation on CSoC”, in proceedings of IEEE-TTTC International Conference on Automation, Quality and Testing, Robotics (A&QT-R), 2002.

  8. G. Asadi, S.G. Miremadi, S. Bayat Sarmadi, and A. Ejlali, “Speeding up Design Verification Using Co-Operation of Simulation and Emulation”, in the proceeding of the IEEE-TTTC International Conference on Automation, Quality and Testing, Robotics (AQTR), 2002.